Soft Machines (startup with $125 million in funding and working with Samsung and AMD) developed new VISC™ (Virtual Instruction Set Computing) Architecture (19 page presentation)
Soft Machines demonstrated a 28nm dual-core version of their virtual core approach at the Linley Processor Conference. The 300-400MHz prototype chip ran 32-bit ARM software at performance levels that suggest its technology could provide a leap over current approaches. It looked impressive and could be the gist of a first product.
The startup aimed for 10x improvements but on average expects to deliver still respectable 4x gains. The good news is its technology could be applied to a broad range of chips, from IoT and mobile SoCs to server processors.
The next big target is a quad-core version running at about 1.5 GHz.
• Extracting ILP has significant complexity
• OoO complexity increases quadratically with machine width
• VISC complexity increases linearly with number of virtual cores
• VISC Performance/Watt utilizes linear scaling
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Soft Machines demonstrated a 28nm dual-core version of their virtual core approach at the Linley Processor Conference. The 300-400MHz prototype chip ran 32-bit ARM software at performance levels that suggest its technology could provide a leap over current approaches. It looked impressive and could be the gist of a first product.
The startup aimed for 10x improvements but on average expects to deliver still respectable 4x gains. The good news is its technology could be applied to a broad range of chips, from IoT and mobile SoCs to server processors.
The next big target is a quad-core version running at about 1.5 GHz.
• Extracting ILP has significant complexity
• OoO complexity increases quadratically with machine width
• VISC complexity increases linearly with number of virtual cores
• VISC Performance/Watt utilizes linear scaling
Read more »
